Output driver circuits are frequently configured to have impedance matching characteristics that enable off-chip loads to be driven more efficiently. FIG. 1 illustrates a conventional impedance-matched output driver circuit 10 having a totem pole arrangement of PMOS pull-up transistors and NMOS pull-down transistors therein. As illustrated, a pull-up path of the driver circuit 10 includes a plurality of PMOS pull-up transistors, shown as MP0 and MP1, and a pull-down path of the driver circuit 10 includes a plurality of NMOS pull-down transistors, shown as MN0 and MN1. The PMOS pull-up transistor MP0, which is responsive to an active low input signal PUX, operates as a pass transistor that becomes active when an output terminal (OUT) of the driver circuit 10 is to be switched low-to-high. However, the PMOS pull-up transistor MP1 may comprise a plurality of parallel-connected PMOS transistors that are responsive to respective bits of a multi-bit pull-up control signal. This multi-bit pull-up control signal, which is an active low signal, is shown as PUX—CODE. In some cases, the plurality of parallel-connected PMOS transistors may represent an array of binary weighted transistors that are selectively enabled to match impedance characteristics of a load (not shown) connected to the output terminal OUT. The value of the pull-up control signal PUX—CODE may be updated periodically to maintain the impedance matching characteristics of the driver circuit 10.
The NMOS pull-down transistor MP0, which is responsive to an active high input signal PD, operates as a pass transistor that becomes active when an output terminal OUT of the driver circuit 10 is to be switched high-to-low. The NMOS pull-down transistor MN1 may comprise a plurality of parallel-connected NMOS transistors that are responsive to respective bits of a multi-bit pull-down control signal. This multi-bit pull-down control signal, which is an active high signal, is shown as PD—CODE. The plurality of parallel-connected NMOS transistors may represent an array of binary weighted transistors that are selectively enabled to match impedance characteristics of the load. The value of the pull-down control signal PD—CODE may be updated periodically to maintain the impedance matching characteristics of the driver circuit 10.
As will be understood by those skilled in the art, the pass transistors MP0 and MN0 will go into saturation before the output terminal OUT switches through ½VDDQ, when VDDQ, which is the power supply voltage, is reduced. As illustrated by the I-V curve of FIG. 2, when the output terminal OUT of the driver circuit 10 of FIG. 1 is swept from GND to VDDQ, a highly nonlinear I-V characteristic is observed after the voltage of the output terminal (VOUT) exceeds about ½VDDQ, where VDDQ=1.5 Volts. Furthermore, the speed of the driver circuit 10 may be limited by the fact that both the pull-up and pull-down paths include a serial connection of two transistors, which means that relatively large transistors are required to maintain sufficiently high switching speed.
FIG. 3 illustrates another conventional driver circuit 12 that includes two parallel pull-up paths and two parallel pull-down paths. The pull-up paths include the series combination of PMOS transistors MP0 and MP1 in parallel with PMOS transistor MP2. The pull-down paths include the series combination of NMOS transistors MN0 and MN1 in parallel with NMOS transistor MN2. The PMOS transistor MP0 and the NMOS transistor MN0 are configured as MOS diodes, which operate to improve the linearity of the driver circuit 12. However, because two of the transistor gates are connected to the output terminal OUT, the driver circuit 12 of FIG. 3 may have relatively poor electrostatic discharge (ESD) characteristics and relatively high output capacitance. The ESD characteristics of the driver circuit 12 may be improved by adding resistors at the gate terminal of PMOS transistor MP0 and gate terminal of NMOS transistor MN0, however this will result in an RC delay that may limit voltage tracking between the gate terminals of the transistors MP0 and MN0 and the output terminal OUT. The use resistors for ESD protection in output driver circuits is also disclosed in an article by Y. Fan et al., entitled “On-Die Termination Resistors with Analog Impedance Control for Standard CMOS Technology,” IEEE Journal of Solid-State Circuits, Vol. 38, No. 2., pp. 361–364, February (2003). In particular, FIG. 3 of the Fan article illustrates an analog on-die termination (ODT) bias generator that provides a bias signal to an output driver having an ODT unit therein.
Notwithstanding these conventional output driver circuits, there continues to be a need for driver circuits having enhanced operating characteristics.